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NXP Semiconductors /LPC43xx /ADCHS /POWER_CONTROL

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Interpret as POWER_CONTROL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CRS0DCINNEG0DCINPOS0 (TWOS)TWOS 0 (POWER_SWITCH)POWER_SWITCH 0 (BGAP_SWITCH)BGAP_SWITCH 0RESERVED

Description

Configures ADC power vs. speed, DC-in biasing, output format and power gating.

Fields

CRS

current setting for power versus speed programming
DCINNEG

AC-DC coupling selection 0 = No dc bias 1 = DC bias on vin_neg side
DCINPOS

AC-DC coupling selection 0 = No dc bias 1 = DC bias on vin_pos side
TWOS

Output data format selection 0 = offset binary 1 = two’s complement
POWER_SWITCH

0 = ADC is powered down 1 = ADC is active
BGAP_SWITCH

0 = ADC band gap reference is powered down 1 = ADC band gap reference is active
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data